LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux IS
	PORT
	(
		a,b		: IN	STD_LOGIC_VECTOR(7 downto 0);
		sel		: IN 	STD_LOGIC;
		z		: OUT	STD_LOGIC_VECTOR(7 downto 0)
	);
END mux;

ARCHITECTURE arch_mux OF mux IS
	
BEGIN
	process(a,b,sel)
	begin
		IF (sel = '0') THEN
			z <= a;
		ELSE
			z <= b;
		END IF;
	end process;
END arch_mux;